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File information

Name: Microxsafe 6001 G
File name: MS6001_B0_revG.pdf
File size: 0.6 MB

Based on the ARM® SecurCore® SC300™ 32-bit RISC Processor featuring:
- Harvard architecture
- Thumb2® High-code-density Instruction Set
- 3-stage pipeline architecture
- 8-bit,16-bit,32-bit data access
- Nested Vector Interrupt Controller
- Memory Protection Unit